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VIA Nano X2 L4050

Published: (last update )

Core
Code nameIsaiah
Base clock1400 MHz
Turbo full / half / single-
Base multiplier
Technology40 nm
Transistors-
Die size66 mm2
Cores / threads2 / 2
Stepping-
Cache
L1 data cache2 × 64 kB
L1 inst. cache2 × 64 kB
L2 cache2 × 1024 kB
L2 cache typeOn-die, full speed
L3 cache-
L3 cache type-
Instructions
Basic inst.x86, x87, MMX, SSE
Extended inst.SSE2, (S)SSE3
Extended inst. 2x86-64, SSE 4.1
Extended inst. 3VT-x, AES-NI
Extended inst. 4
The CPU
Bus typeQDR, 800 MHz, 64 bit
Bus bandwith6400 MB/s
SocketSocket BGA400
PackageNanoBGA2
Package size21 × 21 mm
Manufacture date-
Voltage0.9 V
TDP27.5 W
Memory controller-
Integrated VGA-
Release date2011
VIA Nano X2 L4050 (front side)

VIA Nano X2 L4050 (front side)

VIA Nano X2 L4050 (back side)

VIA Nano X2 L4050 (back side)