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Cyrix MII-300GP

Published: (last update )

Core
Code nameMII (Cyrix, 300 nm)
Base clock233 MHz
Turbo full / half / single-
Base multiplier3.5×
Technology300 nm
Transistors6.5 million
Die size197 mm2
Density0.033 M / mm2
Cores / threads1 / 1
Stepping-
Cache
L1 data cache64 kB
L1 inst. cache-
L2 cache-
L2 cache typeExternal, 66 MHz
L3 cache-
L3 cache type-
Instructions
Basic inst.x86, x87, MMX
Extended inst.
Extended inst. 2
Extended inst. 3
Extended inst. 4
Extended inst. 5
The CPU
Bus typeSDR, 66 MHz, 64 bit
Bus bandwith528 MB/s
SocketSocket 7
Package296 pin Ceramic PGA
Package size50 x 50 mm
Manufacture date-
Voltage2.9 V
TDP25 W
Memory controller-
Integrated VGA-
Release date1998
Cyrix MII-300GP (front side)

Cyrix MII-300GP (front side)

Cyrix MII-300GP (back side)

Cyrix MII-300GP (back side)