AMD Turion II P520
Published: (last update )
| Core | |
|---|---|
| Code name | Champlain (2C) |
| Base clock | 2300 MHz |
| Turbo full / half / single | - |
| Base multiplier | 11.5× |
| Technology | 45 nm |
| Transistors | 234 million |
| Die size | 118 mm2 |
| Density | 1.98 M / mm2 |
| Cores / threads | 2 / 2 |
| Stepping | DA-C3 |
| Cache | |
| L1 data cache | 2 × 64 kB |
| L1 inst. cache | 2 × 64 kB |
| L2 cache | 2 × 1024 kB |
| L2 cache type | On-die, full speed |
| L3 cache | - |
| L3 cache type | - |
| Instructions | |
|---|---|
| Basic inst. | x86, x87, MMX(+), SSE |
| Extended inst. | 3DNow!, SSE2, SSE3 |
| Extended inst. 2 | x86-64, SSE4a |
| Extended inst. 3 | AMD-V |
| Extended inst. 4 | |
| Extended inst. 5 | |
| The CPU | |
| Bus type | HT, 3600 MHz, 32 bit |
| Bus bandwith | 14 400 MB/s |
| Socket | Socket S1 (S1g4) |
| Package | 638 pin lidless organic micro PGA |
| Package size | 35 x 35 mm |
| Manufacture date | 29th week of 2010 |
| Voltage | 1.1 V |
| TDP | 25 W |
| Memory controller | DDR3 1066, 128 bit |
| Integrated VGA | - |
| Release date | 2010 |
