AMD Ryzen 3 1200
Published: (last update )
Note: The Summit Ridge die contains two CCX - 4C/8T and 8 MB L3 cache each. Ryzen 3 1200 has 2 cores and 4 MB of L3 cache enabled per CCX. SMT is disabled.
| Core | |
|---|---|
| Code name | Summit Ridge |
| Base clock | 3100 MHz |
| Turbo full / half / single | 3100 | 3100 | 3400 MHz |
| Base multiplier | 31× |
| Technology | 14 nm |
| Transistors | 4800 million |
| Die size | 213 mm2 |
| Density | 22.5 M / mm2 |
| Cores / threads | 4 / 4 |
| Stepping | ZP-B1 |
| Cache | |
| L1 data cache | 4 × 32 kB |
| L1 inst. cache | 4 × 64 kB |
| L2 cache | 4 × 512 kB |
| L2 cache type | On-die, full speed |
| L3 cache | 2 × 4096 kB |
| L3 cache type | On-die, full speed |
| Instructions | |
|---|---|
| Basic inst. | x86, x87, MMX(+), SSE |
| Extended inst. | SSE2, (S)SSE3 |
| Extended inst. 2 | x86-64, SSE(4.1, 4.2, 4a) |
| Extended inst. 3 | AMD-V, AES-NI, AVX |
| Extended inst. 4 | AVX2, FMA3 |
| Extended inst. 5 | |
| The CPU | |
| Bus type | UMI, 100 MHz |
| Bus bandwith | - |
| Socket | Socket AM4 |
| Package | 1331 pin lidded micro PGA |
| Package size | 40 x 40 mm |
| Manufacture date | 42nd week of 2017 |
| Voltage | - |
| TDP | 65 W |
| Memory controller | DDR4 2666, 128 bit |
| Integrated VGA | - |
| Release date | 2017 |
