AMD K6, K6-2, K6-III, K6-III+
K6's main competitor was Pentium MMX and later Pentium II. AMD bought the architecture from NextGen - Nx686 processor. AMD made some adjustments, the most significant one was to make it compatible with socket 7 and adding MMX. First three variants clocked at 166, 200 and 233 MHz became available in April 1997. The best version made it to the market month before Pentium 233 MMX and Pentium II, for the first time AMD held the performance crown.
K6 featured large 64 kB L1 cache split in half for instruction and data cache, just like Intel processors. This had impact on transistors count (8.8 million) and die size of 162 mm2. K6 was manufactured using 350 nm process. The 233 MHz version had power consumption of 30 W which made it difficult to cool properly, especially in AT style cases that lacked proper airflow.
Increasing frequency past 233 MHz was difficult for the original 350 nm K6. Because of that AMD moved to 250 nm technology in January 1998. At first 250 nm K6 dieshrink was introduced and later another improved iteration of the K6 architecture - the K6-2 processor (code name Chomper). K6-2 became very popular, mostly because of compatibility with older socket 7 boards as an upgrade path from Pentium MMX. The biggest advantage of K6-2 was low price of both CPUs and motherboards. Stability and reliability of socket 7 however was worse than socket 370 or slot 1 platforms. Also performance was inferior to Celeron or Pentium II in most cases. The first K6-2 launched in May 1998 at 300 MHz. Over the time with improving manufacturing process AMD managed to increase clock to 550 MHz in year 2000.
K6-2 didn't really differ from 250 nm K6. The only significant change was added 3DNow! instructions. The purpose of 3DNow! was to improve performance in multimedia applications and games to help compensate for weaker FPU than Intel CPUs. Software support was needed to make use of 3DNow! and that took some time. Performance also depended on used motherboard and chipset. The whole socket 7 platform relied on external L2 cache which ran at FSB speed. Especially with faster processors above 300 MHz cache was too slow and reduced performance. Because of that AMD increased FSB frequency (and the cache with it) to 100 MHz. This move alone had noticeable impact on performance. The concept of external cache caused one more limitation. Depending on specific chipset and L2 capacity, the amount of effectively usable RAM was limited. Access to the RAM above cacheable limit was much slower.
|Socket 5/7 chipsets|
|Chipset||L2 cache||RAM type||Max. FSB||Max. RAM||Cacheable RAM||PCI||AGP||Note|
|Intel 430NX||512 kB||FPM||66 MHz||512 MB||512 MB||2.0||no|
|Intel 430FX||512 kB||EDO||66 MHz||128 MB||64 MB||2.0||no|
|Intel 430HX||512 kB||EDO||66 MHz||512 MB||64 / 512 MB||2.1||no||tag RAM dependent|
|Intel 430TX||512 kB||EDO, SDR||75 MHz||256 MB||64 MB||2.1||no|
|Ali Aladdin V (D/E)||512 kB||SDR||100 MHz||768 MB||128 MB||2.1||2×|
|Ali Aladdin V (G)||512 kB||SDR||100 MHz||768 MB||512 MB||2.1||2×||rare|
|Ali Aladdin V (D/E)||1024 kB||SDR||100 MHz||768 MB||128 MB||2.1||2×||rare|
|Ali Aladdin V (G)||1024 kB||SDR||100 MHz||768 MB||1024 MB||2.1||2×||rare|
|VIA MVP3||512 kB||EDO, SDR||100 MHz||768 MB||64 / 128 MB||2.1||2×||WB / WT|
|VIA MVP3||1024 kB||EDO, SDR||100 MHz||768 MB||128 / 256 MB||2.1||2×||WB / WT|
|VIA MVP3||2048 kB||EDO, SDR||100 MHz||768 MB||256 / 512 MB||2.1||2×||WB / WT|
|SiS 530||512 kB||SDR||100 MHz||1536 MB||64 MB||2.1||no|
K6-III, K6-2+, K6-III+
Few days before Pentium III, AMD introduced another K6-based product. K6-III was much like the older K6-2, except one thing - 256 kB of on-die L2 cache running at full-speed (400 or 450 MHz). That was step in the right direction, large and fast cache allowed to overcome weak memory access caused by relatively slow chipsets. Performance increased by dozens of percent. Of course integrating L2 cache took it's price - 21.3 million transistors manufactured on 250 nm technology was close to the limit. Therefore K6-III never reached frequency higher than 450 MHz, a full 100 MHz lower than less advanced K6-2.
In 2000 the very last iteration of K6 architecture showed up - K6-2+ and K6-III+ processors. It was dieshrink of the original K6-III made on the new 180 nm process. Both processors were originally meant for laptops but socket 7 package remained. Most desktop boards could provide voltage around 2V, so it was possible to run these chips in desktop PC too. Especially K6-2+ was popular. Half of the L2 cache was deactivated, but even 128 kB of on-die L2 was enough to reach performance level of K6-III(+). The 180 nm technology lowered power consumption greatly, however frequency rose only slightly. The fastest K6-2+ reached 570 MHz. The K6 architecture simply wasn't optimized for high clock. All K6 with on-die L2 cache could still use external onboard cache. It was the first time three levels of cache appeared in the x86 world. Also all of these processors overcame the cacheable RAM limit, they could access the RAM using their own L2 cache and use the whole installed capacity.
The K6 architecture couldn't match Pentium II/III performance and maximum clock was limited to approximately 600 MHz. AMD had to come up with something better. In June 1999 AMD introduced brand new architecture K7 and Athlon processor based on it. Athlon managed to beat equally clocked PIII Katmai and even for later Coppermine it was worthy competitor. In games above all, which was Intel's stronghold until Athlon. Interesting element of the new architecture was DDR FSB cocked effectively at 200 MHz. Bandwidth between the processor and chipset reached 1600 MB/s - much more than 800 or 1066 MB/s in case of Pentium III.
Obviously socket 7 wasn't suitable for K7. Athlon just like PII/III utilized 512 kB of external L2 cache running at half speed of the core. In order to save cost, AMD used the same SECC-1 package like Pentium II did. Electrically AMD's and Intel's bus wasn't compatible of course. Therefore new slot A had different key placement to avoid inserting Athlon to Intel boards and vice versa.
First Athlon models ran at 500, 550 and 600 MHz, all of them were introduced early summer 1999. Later 650 and 700 MHz Athlon appeared. All of them were made using 250 nm technology (code name Argon). The core didn't integrate L2 cache, but nevertheless transistor count was 22 million and die size 184 mm2. Most likely this was caused by very large and fast L1 cache (64 kB instruction + 64 kB data cache). Also power consumption was rather high (around 50W), but given the great performance it was acceptable. Later AMD dieshrinked Athlon to 180 nm (code name Pluto), it somewhat decreased power consumption and allowed AMD to run Athlon at higher clock.
Cyrix 6x86, MII, IDT Winchip
Cyrix 6x86, MII
Just like many other x86 CPU manufacturers, Cyrix was also busy making 486 processors. Most of the time, they were cheaper and worse performing alternatives to i486. In 1995 Cyrix presented 6x86, competition for Intel Pentium and AMD K5. Architecture was more advanced compared to the Pentium and in some applications (office applications in particular) 6x86 was faster. Because of this, Cyrix came up with Pentium Rating. Processors marking suggested higher frequency than 6x86 actually ran at, usually one step more. For example 6x86 PR166+ only ran at 133 MHz. The real-life performance of 6x86 greatly depended on application it was running. Especially when using FPU, Pentium was much better and PR rating was overly optimistic. Another disadvantage was heat production and cooling problems. Cyrix addressed it with improved 6x86L (code name M1L). Lowered voltage from 3.5V to 2.8V lowered heat amount to half. The fastest 6x86 model was the PR200+ running at 150 MHz in 1996.
One year later Cyrix was ready to present 6x86 successor - 6x86MX. L1 cache was quadrupled from 16 to 64 kB (but still remained shared for instruction and data). Also MMX instructions were added and new 300 nm manufacturing process was used to make 6x86MX. Cyrix continued to use Pentium Rating. This time not only core clock determined PR, but also bus speed. Other than standard 66 MHz, some 6x86MX versions ran at 75 or 83 MHz FSB. This led to somewhat better performance however also compatibility and stability issues on some motherboards. Original 6x86MX existed in PR166 (133 MHz) to PR233 (188 MHz). Later the 6x86MX was renamed to Cyrix MII. Architecture remained unchanged, only frequency and manufacturing technology improved over time. MII PR433 running at 300 MHz made using 180 nm technology was the last CPU made by Cyrix. At the time VIA bought Cyrix and canceled development of high performance CPUs.
The last of well-known x86 CPU manufacturers was IDT. All IDT processors were designed with emphasis on low power consumption and price. In the end of 1997 Winchip C6 arrived to market, it was the first x86 compatible processor from IDT. There were four variants in total - 180, 200, 225 and 240 MHz. The latter two were launched in April 1998. All Winchip C6 were made using 350 nm technology, contained of 5.4 million transistors and used socket 7. Even though transistor count was bigger that in case of Pentium MMX for example, the architecture was very simple and L1 cache (32 + 32 kB) took most of the transistor budget. Winchip C6 supported MMX, however it didn't bring good performance. Its architecture was simply too poor compared to the competition. The Winchip core was in fact very similar to the 486 - featured only one pipeline and didn't support Out-of-Order execution. 6x86, K5, K6, P6 and even P5 were much more advanced.
During 1998 and 1999 improved versions of Winchip were introduced. Winchip 2 added 3DNow! support, Winchip 2A used 100 MHz FSB for some models. Everything else remained unchanged and thus performance didn't improve much. At the time K6-2 and Celeron were very common and compared to them Winchip looked very poor. Winchip 2B was planned and also Winchip 3, none of them made in to the market. In the end of 1999 VIA bought Centaur Technology, this meant the end of Winchip brand. Not the end of Centaur architecture however - VIA used it for a long time in Cyrix III, VIA C3 and VIA C7 processors.